1. Field of the Invention
The present invention relates to a component-embedded board in which an electronic component is provided in a multilayer board, and the invention also relates to a communication terminal device including the same.
2. Description of the Related Art
An example of a conventional component-embedded board is described in Japanese Laid-Open Patent Publication No. 2011-222553. In this component-embedded board, an electronic component (semiconductor chip), which has stud bumps provided on electrodes on a first surface, and a thermosetting resin film (first layer), which has pads formed thereon, are disposed such that the stud bumps are opposite to the pads with a thermoplastic resin film (second layer) positioned therebetween. Here, the pads and the stud bumps as well as the electrodes and the stud bumps are joined by a pressing and heating process.
Furthermore, provided on the second layer is a thermosetting film (third layer) with a hollow portion formed to accommodate the electronic component. The electronic component has another group of electrodes for wiring or thermal radiation provided on a second surface on the opposite side to the first surface. Provided on the third layer is a thermoplastic resin film (fourth layer) in which interlayer connectors are formed and joined to the group of electrodes provided on the second surface of the semiconductor chip.
In the component-embedded board, interlayer connectors formed in the first layer are electrically connected to interlayer connectors formed in the second layer via pattern conductors. Likewise, interlayer connectors of the third layer are electrically connected to interlayer connectors of the fourth layer via pattern conductors.
On the other hand, the interlayer connectors of the second and third layers are directly bonded to each other without any pattern conductors being interposed there between. Here, the second layer is provided with at least one interlayer connector outside each of two opposing sides of the first surface (or the second surface) of the semiconductor chip. The interlayer connectors of the third layer, when viewed in a plan view in the direction of stacking from the first layer to the fourth layer, are provided in the same positions as the interlayer connectors of the second layer.
As described above, the interlayer connectors of the second and third layers are simply provided outside two opposing sides of the electronic component. Accordingly, when the layers are pressed in the stacking direction at the time of the pressing and heating process, the interlayer connectors of the second and third layers might be misaligned from each other.